Power Aware Computing

Student:Stefan Büttcher
Title:Power Aware Computing
Type:diploma thesis
Advisors:Veldema, R.; Philippsen, M.
State:submitted on February 6, 2004

Compiler transformations that insert Dynamic Voltage Scaling (DVS) system calls into selected regions of the code. The basic idea comes from Ulrich Kremer and his colleages at Rutgers university: They analyzed code (before compilation) and searched for sections of code whose performance seem bounded by memory latency rather than by CPU performance. In those sections of code, which in most cases are loop nests with high loads of memory access, CPU frequency and voltage can be reduced in order to save energy at very little performance cost.
Kremer et al, employed some techniques that could be improved upon: First, they perform compile-time profiling in order to determine which regions are best suited for DVS and which frequency should be selected. This means that the program has to be fed with representative input data at compile time, which in many cases is not available. Second, they assume a system with only one active task that has full control over the system's voltage and frequency settings. On most operating systems, this is not true and can have serious impacts on program performance, since there might be several programs running in parallel, each having its own voltage/frequency settings...

This thesis, will entail the development of a source code analyzer that tries to find program regions that seem to be good candidates for DVS and inserts DVS API calls, but:

  • the API calls have no constant effects but are only suggestions to the kernel: "you should lower the frequency now", so that several parallel tasks do not disturb each other,
  • there is no profiling performed at compile-time; instead, the kernel attempts to lower the CPU frequency at run-time and in turn receives feedback from the application (via the sys calls inserted by the compiler) on how much the program performance has been affected by lowering the frequency,
  • most of the algorithm's logic is located in the scheduler inside the OS kernel and is executed at run-time. However, the compiler takes arguments such as "we do not want a slowdown of more than 5%" or "this application is not a real-time application" that help the kernel to determine the optimal frequency/voltage pair.
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