ORKA-HPC - OpenMP for reconfigurable heterogenous architectures

Director:Philippsen, M.
Period:November 1, 2017 - October 31, 2020
Coworker:Mayer, F.
Description:

High-Performance Computing (HPC) is an important component of Europe's capacity for innovation and it is also seen as a building block of the digitization of the European industry. Reconfigurable technologies such as Field Programmable Gate Array (FPGA) modules are gaining in importance due to their energy efficiency, performance, and flexibility.
There is also a trend towards heterogeneous systems with accelerators utilizing FPGAs. The great flexibility of FPGAs allows for a large class of HPC applications to be realized with FPGAs. However, FPGA programming has mainly been reserved for specialists as it is very time consuming. For that reason, the use of FPGAs in areas of scientific HPC is still rare today.
In the HPC environment, there are various programming models for heterogeneous systems offering certain types of accelerators. Common models include OpenCL (http://www.opencl.org), OpenACC (https://www.openacc.org) and OpenMP (https://www.OpenMP.org). These standards, however, are not yet available for the use with FPGAs.

Goals of the ORKA project are:
1.) Development of an OpenMP 4.0 compiler targeting heterogeneous computing platforms with FPGA accelerators in order to simplify the usage of such systems.
2.) Design and implementation of a source-to-source framework transforming C/C++ code with OpenMP 4.0 directives into executable programs utilizing both the host CPU and an FPGA.
3.) Utilization (and improvement) of existing algorithms mapping program code to FPGA hardware.
4.) Development of new (possibly heuristic) methods to optimize programs for inherently parallel architectures.

In 2018, the following important contributions were made:

  • Development of a source-to-source compiler prototype for the rewriting of OpenMP C source code (cf. goal 2).
  • Development of an HLS compiler prototype capable of translating C code into hardware. In the future, this prototype will serve as starting point for the work towards the goals 3 and 4.
  • Development of several experimental FPGA infrastructures for the execution of accelerator cores (necessary for the goals 1 and 2).
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